Speed and accuracy are the two major requirements of analog electronic circuits. Circuit optimization is again in great demand because in general optimization results in contradictory conditions. The speed and accuracy are determined by the settling behavior of the operational amplifier (Op-Amp); fast settling requires high unity gain frequency and accuracy requires a high DC gain. Need to raise the unity gain frequency leads to design of single stage amplifiers with short channel MOS transistors and high bias currents and in contradiction to this high gain requirement leads to multi stage amplifiers with large channel transistors and low bias currents.
A gain boosted technique proposed in “A fast-settling CMOS operational amplifier for SC circuits with 90-db dc gain” by K. Bult and G. Geelen, IEEE Journal of Solid State Circuits, vol. 25, pp. 1379-1394, December 1990, has enabled circuit designers to exploit the advantages of single-stage amplifiers with adequate gain. But with this technique pole-zero doublets are added in the transfer function of the op-amp which does not noticeably affect the frequency response of the amplifier but which introduces a very slow settling component in the settling response which can adversely affect the accuracy of the whole device.
Therefore, there is a need for an operational amplifier for reducing the settling times and overshooting during the transient response.